The present invention relates generally to the field of semiconductor overlay metrology. More specifically, it relates to techniques for calibrating overlay measurements obtained from a product wafer or device.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the device must be defect free prior to shipment of the device to the end users or customers.
Typically, defects are detected within special test structures or targets, rather than the active device or die itself. By way of example, various targets are designed to measure misalignment or overlay errors between two adjacent layers. Other targets are designed for other purposes, such as measurement of critical dimension or detection of electrical faults or killer defects. There are numerous types of targets on which characteristics may be measured or which may be inspected for defects, e.g., by comparing to an ideal reference target to the target under inspection.
Although these targets are used to estimate yield or defect density within the active area, the targets are typically relegated to special test areas of the field (e.g., the four outer corners of the field perimeter or scribe line). That is, the targets are not located within the same area as the functioning or active device. Conventional positioning of targets outside the active areas allows one to dedicate product space to product features. It has been undesirable to utilize active area space for nonfunctioning structures because engineers are constantly striving to maximize active feature density.
Unfortunately, a test structure positioned in the four corners of the exposure tool field or the scribe line does not best represent product function or typical variations across the field of the lithography (or exposure) tool. Multiple dies are exposed in a single field of the lithography tool. Although the scribe lines may extend across the wafer, these scribe lines may not extend across the field. Accordingly, defects captured or measured within the targets may not be a good indicator of defects within the product area or die itself. In a specific case, the lithography tool usually contains aberrations in its lens system which result in feature misalignments or pattern placement errors across the field. Even if a test structure is placed in each field (such as in the center of each die), a manufacturing process may be different for different areas of the product area, as opposed to the test area. For instance, the process may vary with position of the feature in the field. By way of specific example, product feature may be located at a different position of the field than the target feature areas and, accordingly, print differently than the target feature areas. Thus, deviations or defects which depend on feature field position are not captured by placing targets in special test areas because the targets do not correspond to a position within the field which is representative of the product feature.
Accordingly, it would be desirable to have targets which more reliably and accurately represent defects within the active or product region. Additionally, targets which capture deviations across the lithography field are desired.